Programmable logic devices (“PLDs”) are reconfigurable digital circuits, such as, for example, an erasable programmable read-only memory (“EPROM”), an electrically-erasable read-only memory (“EEPROM”), a programmable array logic (“PAL”), a complex programmable logic device (“CPLD”), a field-programmable gate array (“FPGA”), and the like. A single PLD can replace tens, hundreds, or even thousands of logic gates with a single integrated circuit.
Various techniques have been used to configure PLDs. For example, an EPROM is a non-volatile memory (i.e., it retains its configuration when power is turned off) that is typically erased by exposure to ultraviolet light, and programmed out-of-circuit using a device having a socket to receive the EPROM. A higher programming voltage is applied and a configuration is loaded and retained until the EPROM is erased and/or reprogrammed. While this technique works for PLDs having non-volatile memory, not all PLDs retain their configurations when powered down, such as, for example, FPGA (field programmable gate array) devices.
FPGA devices are traditionally configured using a local, non-volatile memory with static signal connections. During power-up, a configuration stored in the non-volatile memory or data storage device (e.g., a flash memory, hard drive, and the like) is loaded into the FPGA. Configuration information may be sent to an FPGA in parallel, loading multiple bits (usually one or more bytes) simultaneously, or it may be sent serially.
One way to configure an FPGA serially is by using extensions to a testing standard designed to facilitate and improve circuit-level testing that was developed by JTAG (“Joint Test Action Group”) and standardized as IEEE 1149.1-2001 (commonly referred to as “JTAG”). Conventional testing of assembled printed circuit boards (“PCBs”) involved placing the boards on a “bed of nails,” forming an electrical connection between a testing device and each junction on the PCB. In this manner, the testing device could insert signals anywhere on the board and measure electrical properties (such as resistance and voltage). With the advent of multi-layer PCBs and surface-mounted components, the bed-of-nails testing approach proved inadequate. JTAG was formed to develop a testing standard adequate to handle developing technology. The JTAG solution was to place boundary cells around each component to be tested. These boundary cells are then serially chained together.
Xilinx™ offers a configuration solution called the Xilinx System ACE™, which uses an integrated circuit to configure any number of FPGAs using configuration data stored on a CompactFlash device or other non-volatile data storage device. Using the Xilinx™ solution, FPGAs are connected together in a JTAG chain and configuration data is serially passed from FPGA to FPGA.
FIG. 1 shows a system using JTAG-based PLD configuration, such as that used by Xilinx™ for FPGAs. In this system, a configuration controller 101 communicates with a configuration storage device 103 to retrieve information related to the configuration of a group of PLDs (105a, 105b, 105c) arranged in a JTAG chain. The configuration controller 101 passes the configuration information through the JTAG chain so as to configure each PLD (105a, 105b, 105c) in the chain.
While systems, such as that shown in FIG. 1, generally support the configuration of multiple PLDs (105a, 105b, 105c), they typically require that each PLD (105a, 105b, 105c) in a chain be powered up. As the number of PLDs used in digital systems increases, there is an increasing need for greater flexibility and control in PLD configuration.